RP2040 is the debut microcontroller from Raspberry Pi. It brings its signature values of high performance, low cost, and ease of use to the microcontroller space. With a large on-chip memory, symmetric dual-core processor complex, deterministic bus fabric, and rich peripheral set augmented with our unique Programmable I/O (PIO) subsystem, it provides professional users with unrivaled power and flexibility.

Flexible I/O connects RP2040 to the physical world by allowing it to speak to almost any external device. High-performance breezes through integer workloads. Low cost helps ease the barrier to entry.

This isn’t just a powerful chip: it’s designed to help you bring every last drop of that power to bear. With six independent banks of RAM and a fully connected switch at the heart of its bus fabric, you can easily arrange for the cores and DMA engines to run in parallel without contention.

RP2040 builds Raspberry Pi’s commitment to inexpensive, efficient computing into a small and powerful 7 mm × 7 mm package, with just two square millimeters of 40 nm silicon.

With detailed documentation, a polished MicroPython port, and a UF2 bootloader in ROM, it has the lowest possible barrier to entry for beginner and hobbyist users. RP2040 is a stateless device, with support for cached execute-in-place from external QSPI memory.

This design decision allows you to choose the appropriate density of non-volatile storage for your application, and to benefit from the low pricing of commodity Flash parts. RP2040 is manufactured on a modern 40nm process node, delivering high performance, low dynamic power consumption, and low leakage, with a variety of low-power modes to support extended-duration operation on battery power.

Features-

CPU: Dual ARM Cortex-M0+ @ 133 MHz

Memory: 264kB on-chip SRAM in six independent banks Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus.

Architecture: DMA controller, fully connected AHB crossbar, Interpolator and integer divider peripherals, on-chip programmable LDO to generate core voltage, two on-chip PLLs to generate USB and core clocks.

Interface: 30 GPIO pins, four of which can be used as analogue inputs.

Peripherals: 2 × UARTs, 2 × SPI controllers, 2 × I2C controllers, 16 × PWM channels,      1 × USB 1.1 controller and PHY, with host and device support & 8 × PIO state machines

Package: 7 × 7 mm QFN-56 package

Specification-

• Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz
• 264KB on-chip SRAM
• 2 × UART, 2 × SPI controllers, 2 × I2C controllers, 16 × PWM channels
• 1 × USB 1.1 controller and PHY, with host and device support
• 8 × Programmable I/O (PIO) state machines for custom peripheral support
• Supported input power 1.8–5.5V DC
• Operating temperature -20°C to +85°C
• Drag-and-drop programming using mass storage over USB
• Low-power sleep and dormant modes
• Accurate on-chip clock
• Temperature sensor
• Accelerated integer and floating-point libraries on-chip